High-performance semiconductor devices often incorporate one or more layers of substantially crystalline semiconductor materials. Highly efficient III-V multi-junction photovoltaic solar cells incorporate III-V crystalline semiconductor materials such as GaInAs and GaInAlP alloy that are produced using epitaxy on single crystal Ge or GaAs substrates. High efficiency light emitting diodes (LEDs) and diode lasers may be fabricated from epitaxially grown nitride semiconductors such as InGaN. High electron mobility transistors may incorporate epitaxially grown arsenide or antimonide semiconductor materials such as InAs and InSb.
The semiconductor materials used in these high-performance semiconductor devices are typically selected based on optoelectronic performance criteria such as the specific band gap or electron mobility of the material. The function of these semiconductor devices is essentially governed by the optoelectronic properties and arrangement of the device's semiconductor materials. Further, the quality of the crystalline semiconductor materials of these devices impact their overall performance; defects, impurities and other flaws in the crystalline structure of the semiconductor materials may degrade the performance of the semiconductor devices.
Typically, high-performance semiconductor devices are fabricated using an epitaxial growth process in which a monocrystalline semiconductor material is deposited on a monocrystalline substrate material. However, the ability to produce low defect density crystals of the semiconductor materials used in high-performance semiconductor devices is constrained by several factors. Typically, the crystal lattice dimensions of the substrate must be closely matched to the corresponding lattice of the epitaxially deposited semiconductor material in order to avoid lattice mismatching that may introduce internal stresses and resultant undesired defects in the semiconductor material. Further, if the thermal expansion properties of the substrate material are significantly different from the corresponding thermal expansion properties of the semiconductor material, the temperature range experienced by the device during typical epitaxial growth processes may induce differential swelling and shrinking of the substrate material relative to the deposited semiconductor material, resulting in cracking and other undesired defects.
Existing semiconductor fabrication methods use a number of approaches to avoid the development of defects in the crystalline semiconductor materials. In many methods, the substrate material may be lattice-matched to the deposited semiconductor material. For example, III-V multi-junction photovoltaic cells may be grown on a Ge or GaAs substrate that is lattice-matched to the deposited III-V alloy semiconductor materials of the device. However, many of the substrate materials that are lattice-matched to desirable III-V semiconductor materials may be difficult to obtain in single-crystal form of suitable quality, may be relatively rare or prohibitively expensive, or may be difficult to obtain or produce in large quantities or suitable sizes. In the case of some III-V semiconductors, such as the InGaN alloys used in high-performance LEDs, a suitable lattice-matched substrate may not exist.
To reduce the stresses introduced by a lattice mismatch between the substrate and the deposited semiconductor material, some existing fabrication methods make use of a series of graded buffer layers, in which the lattice of the buffer layer closest to the substrate is slightly mismatched with the lattice of substrate, and the uppermost buffer layer is only slightly mismatched with the semiconductor material to be deposited. The intermediate buffer layers are designed to gradually transition from the buffer lattice dimensions to the semiconductor lattice dimensions, and the number of buffer layers used depends in part upon the degree of lattice mismatch between the substrate and the semiconductor. However, stresses may still occur between successive buffer layers that may result in defects that may impact device performance. In addition, the introduction of graded buffer layers between the substrate and the deposited semiconductor may result in added process complexity and expense, and the introduction of impurities that may also impact device performance.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.